A commonly used method for processing metal oxide semiconductor (MOS) transistors and bipolar transistors in integrated circuits at a major surface of a semiconductive silicon body (substrate) involves the local oxidation of silicon (LOCOS) process for electrically isolating neighboring transistors. In that process, the major surface of the silicon substrate is masked with a silicon nitride layer having (rectangular) window areas, and the exposed silicon in these window area is oxidized. However, owing to lateral oxidation of silicon under the silicon nitride mask, the LOCOS process undesirably increases the required distance between neighboring transistors, whereby the transistor packing density is undesirably reduced.
In order to avoid the aforementioned disadvantage of the LOCOS process, selective epitaxial growth (SEG) of silicon has been proposed as an alternative. In SEG, an epitaxial layer of semiconductive silicon is grown on the exposed portions of the major surface of a semiconductive silicon body, these exposed portions being located at the bottom of windows in an insulating layer located on the major surface of the silicon body. At the same time, no silicon accumulates on the insulating layer--hence the use of the word "selective" in SEG. However, in prior art a major problem associated with SEG is the unwanted formation of facets at the corners of the windows, whereby significant portions of the overall resulting surface of the SEG silicon become undesirably non-planar, so that the transistor packing density again is reduced. For example, when fabricating an MOS transistor on a major surface of SEG silicon grown on silicon which is oriented (100), the undesired facets are oriented (311), these facets being undesired because it is desirable that the active region of the gate of the transistor everywhere be confined to areas overlying the portion of the major surface oriented (100).
In U.S. Pat. No. 4,786,615 entitled "Method for Improved Surface Planarity in Selective Epitaxial Silicon," issued to Liaw et al on Nov. 22, 1988, a method for SEG of silicon by chemical vapor deposition (into an assumedly rectangular window) was disclosed, in order to obtain a substantially planar epitaxial silicon surface. In that method, superimposed epitaxial silicon layers were grown in windows penetrating through a masking layer at temperatures above and below a transition point. The masking layer could be a single layer of insulating material, such as silicon dioxide, or it could be multilayered mask, such as silicon dioxide located on doped polysilicon located on silicon dioxide. That method, however, requires careful control over temperature vs. time, which can be disadvantageous.
Accordingly, it would be desirable to have a method for SEG of semiconductive silicon or other semiconductor, which does not suffer from the disadvantage of prior art.